Omitting Cache Look-Up for High-Performance, Low-Power Microprocessors
نویسندگان
چکیده
In this paper, we propose a novel architecture for low-power direct-mapped instruction caches, called “historybased tag-comparison (HBTC) cache”. The cache attempts to reuse tag-comparison results for avoiding unnecessary tag checks. Execution footprints are recorded into an extended BTB (Branch Target Buffer). In our evaluation, it is observed that the energy for tag comparison can be reduced by more than 90 % in many applications. key words: cache, low power, look up, run time
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